Most switched-capacitor analog circuits such as switched-capacitor filters, analog-to-digital converters, and delta-sigma modulators require precise sampling of analog voltages on a capacitor. The charge sampled on the sampling capacitor must be a precise linear function of the voltage that has been sampled. A basic sampling circuit is illustrated in FIG. 1.
The MOS transistor M1 is operated as a switch. When the gate voltage Vg is high, MOS transistor M1 is turned ON, and the output voltage Vout is equal to the input voltage Vin. The charge, q, on the sampling capacitor CL is equal to VinCL.
When Vg goes low, MOS transistor M1 turns OFF, and sampling capacitor CL is isolated from the input. If MOS transistor M1 were an ideal switch, the charge, q, sampled on sampling capacitor CL would remain unaltered. However, the MOS transistor M1 is not an ideal switch and thus injects MOS transistor M1 charge onto sampling capacitor CL.
Part of the injected charge is from the channel charge, and the rest is due to capacitive coupling from the gate terminal of MOS transistor M1 to the output node. The capacitive coupling generally gives a constant offset error and does not give rise to nonlinearity. The channel charge in MOS transistor M1 splits into two components, q1 and q2, when MOS transistor M1 is turned OFF. The component q2 causes an error with respect to the charge, q, on the sampling capacitor CL. In other words, the charge, q, on the sampling capacitor CL is equal to VinCL+q2.
The channel charge in MOS transistor M1 is a function of the input voltage because the gate-to-source voltage Vgs of MOS transistor M1 is equal to Vg−Vin.
It is well known that the channel charge of a MOS transistor is a nonlinear function of the gate-to-source voltage. Since the channel charge is a nonlinear function of the input voltage, the resulting charge error is a nonlinear function of the input voltage.
Conventionally, ground-side sampling, as illustrated in FIG. 2, removes the input dependence of the charge injection in the first order. In the sampling circuit, shown in FIG. 2, two MOS transistors are employed, the source-side transistor M1 and the ground-side transistor M2. When both transistors, M1 and M2, are turned ON, the input voltage Vin is applied across the sampling capacitor CL. The sample is taken when the gate voltage Vg2 of the ground-side transistor M2 is lowered, thereby turning ground-side transistor M2 OFF. The channel charge in ground-side transistor M2 splits into two components as before, q1 and q2, when ground-side transistor M2 is turned OFF. The component q2 causes an error with respect to the charge, q, on the sampling capacitor CL. In other words, the charge, q, on the sampling capacitor CL is equal to VinCL−q2.
In contrast to the circuit of FIG. 1, the channel charge in ground-side transistor M2 is independent of the input voltage Vin, at least to the first order. This is because the source and the drain voltages are at ground potential when ground-side transistor M2 is ON. Thus, if the ratio of the channel charge split between q1 and q2 is constant, the charge error, q2, will be constant rather than a nonlinear function of the input voltage. Such a constant offset error can be readily removed or minimized.
For high accuracy application, even a small amount of nonlinearity in q2, due to second order effects, is often a limiting factor. For example, the channel charge in ground-side transistor M2 may be dependent of the input voltage Vin due to a second order effect.
The second order effect is due to the impedance variation in source-side transistor M1. The ON resistance of source-side transistor M1 varies with the input voltage Vin. In addition, the parasitic capacitance associated with source-side transistor M1 is a nonlinear function of the input voltage Vin.
In FIG. 3, the variable ON resistance of source-side transistor M1 is shown as RON, and the variable parasitic capacitance CP. As the gate voltage Vg2 is lowered to turn OFF ground-side transistor M2, the channel charge splits into q1 and q2. This process is not instantaneous, but takes a finite amount of time on the order of the transit time of carriers in ground-side transistor M2.
As q2 leaves ground-side transistor M2, current, corresponding to i=dq2/dt, flows into the network consisting of CL, RON, and CP. This current creates a time-dependent voltage at the drain node of ground-side transistor M2, in turn creating an electric field between the drain and the source of ground-side transistor M2. This effect alters the split ratio between q1 and q2. Since the time-dependent voltage on the drain of ground-side transistor M2 is a function of the composite impedance given by CL, RON, and CP, the charge split ratio between q1 and q2 is dependent on the input voltage Vin. Since RON, and CP are nonlinear functions of the input voltage Vin, the injected charge q2 is a nonlinear function of Vin.
Although source-side transistor M1 and ground-side transistor M2 are shown as NMOS transistors in FIG. 2, a parallel connection of NMOS and PMOS transistors, commonly referred to as a complementary switch, is often conventionally employed. The complementary switches somewhat alleviate the nonlinear charge injection, but not to a satisfactory extent with respect to utilization in high accuracy circuits.
It is noted that if the time constant, RONCP, is much faster than the carrier transit time, the impedance presented by RON dominates within the time scale of the charge injection. In this situation, the instantaneous incremental voltages v1 and v2 at Nodes 1 and 2, respectively, are v1=(dq2/dt)RON and v2=v1+(q2/CL)=(dq2/dt)RON+(q2/CL).
On the other hand, if the time constant, RONCP, is much slower than the carrier transit time, the impedance presented by CP dominates within the time scale of the charge injection. In this situation, the instantaneous incremental voltages v1 and v2 at Nodes 1 and 2, respectively, are v1=q2/CP and v2=v1+(q2/CL)=q2/CP+q2/CL=q2(1/CP+1/CL).
In either situation, the instantaneous changes in v2 create an electric filed across ground-side transistor M2. This effect alters the split ratio between q1 and q2 in turn affecting the magnitude of q2. Since v2 is nonlinearly dependent on the input voltage Vin through either RON or CP, the resulting q2 is also a nonlinear function of the input voltage Vin.
Therefore, it is desirable to provide a sampling circuit that accurately samples an input voltage without suffering from the nonlinear error introduced by charge injection. It is desirable to provide a sampling circuit that accurately samples an input voltage without suffering from the nonlinear error introduced by charge injection and provides differential signal paths for sampled-data circuits. Furthermore, it is desirable to provide a sampling circuit that reduces the effect of power supply, substrate, and common-mode noise by symmetric differential signal processing. Also, it is desirable to provide a sampled-data circuit that increases the signal range by incorporating differential signal paths.